The present invention relates to a semiconductor device and, more particularly, to a technology which is effective when applied to a semiconductor device formed with a well in a three-layer structure, i.e., a so-called triple well structure which has a deep well of a second conductivity type different from a first conductivity type in a substrate of the first conductivity type, and further has a shallow well of the first conductivity type in the deep well.
For example, Japanese Unexamined Patent Publication No. 2006-303753 (Patent Document 1) describes a logic circuit and an I/O circuit in a semiconductor integrated circuit device having a so-called triple well structure. In the triple well structure, a deep n-well is formed on a p-type semiconductor substrate, and an n-well for forming a p-type MISFET and a p-well for forming an n-type MISFET are formed thereon.
Japanese Unexamined Patent Publication No. Hei 11-97560 (Patent Document 2) discloses a technology which forms, in a nonvolatile semiconductor memory device having a floating gate electrode and a control gate electrode on a semiconductor substrate, an n-well in a p-type semiconductor substrate, forms a p-well in the n-well, forms an antistatic n-type diffusion layer in the p-well, and electrically couples the antistatic diffusion layer and the control gate electrode to prevent the degradation of the reliability of an insulating film due to charging during the processing of an interconnection layer by etching, or prevent a dielectric breakdown therein.
Japanese Unexamined Patent Publication No. 2005-340548 (Patent Document 3) discloses a technology which couples a floating interconnection to a clamp diode to transfer charge that has flown to the floating interconnection to the clamp diode, and thereby prevent a short circuit between the floating interconnection and a ground interconnection adjacent thereto.
Japanese Unexamined Patent Publication No. 2001-358143 (Patent Document 4) discloses a technology for a semiconductor device including at least one interconnection layer including a plurality of relay pins electrically coupled to a plurality of respective gate electrodes, and an uppermost interconnection layer including a plurality of interconnection patterns which are electrically coupled to the plurality of respective relay pins. According to the technology, the gate electrodes are wired using the uppermost-layer interconnection pattern to transfer electrification charge to a region other than the gate electrodes during the etching of the interconnection layers, and thereby prevent the degradation of gate insulating film.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2006-303753    [Patent Document 2]    Japanese Unexamined Patent Publication No. Hei 11-97560    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2005-340548    [Patent Document 4]    Japanese Unexamined Patent Publication No. 2001-358143